1. Field of the Invention
This invention relates to a method for producing integrated circuits having conductor-insulator layers formed thereon; and, more specifically, to a method for producing a dense multilayer metallization pattern on integrated circuits. The invention also relates to an integrated circuit structure with a dense multilayer metallization pattern made with such method.
2. Description of the Prior Art
Integrated circuits are well known devices which provide complicated circuit structures on a single chip. These devices have grown more and more complicated with increasing numbers of devices required for new applications. One technique to meet these requirements is to increase the size of the chips. Another technique is to shrink the size of the individual components of the integrated circuit. Each of these techniques has its problems; and as known techniques for increasing the density of integrated circuits have approached theoretical limits, new methods for increasing the density and complexity of integrated circuits have been sought. One response to these demands is to turn to multilayer interconnection structures in order to afford greater flexibility in arranging the devices on the semiconductor substrates.
One known multilayer interconnection technique is to deposit a first layer of interconnecting metallization on the integrated circuit. Next, an insulating layer is deposited over the first metallization layer. In some cases, the integrated circuit is planarized to a certain extent by the addition of an auxiliary layer of a photoresist and etching the photoresist and the insulating dielectric layer at substantially the same rate to planarize the device (see A.C. Adams, et al., "Planarization of Phosphorus-Doped Silicon Dioxide", J. Electrochem. Soc., Vol. 128, No. 2 (1981), pp. 423 to 429).
Another method which also uses an organic auxiliary layer and a back etching step is disclosed in DE-OS 33 45 040 A1. This method uses as the planarizing layer a polyimide layer which is applied to a metallization pattern on an insulating surface. The entire surface of the polyimide layer is etched back by dry etching to such a depth that the metallization pattern is exposed. Following this step, an inorganic insulating layer is deposited having the desired thickness.
A still improved planarization method is described in EP-A-87106561.1 A1 (0 244 848). According to this method, a metallization pattern is passivated by an inorganic insulating layer, which is conformal with the metallization pattern on the substrate. Next, an organic auxiliary layer is applied to obtain a planar surface. The organic auxiliary layer and the underlying inorganic insulating layer are etched at the same etch rate in a magnetron dry-etching apparatus for a time during which the organic auxiliary layer is completely removed. Next, a second series of inorganic insulating layer and organic auxiliary is applied and etched. This process is surface of the inorganic insulating layer has been achieved.